There are instances where an internal circuit of a semiconductor device is destroyed by electrostatic discharge (ESD) from the outside (from the human body or a machine, etc.). For example, in a MOS field-effect transistor (MOSFET, or Metal Oxide Semiconductor Field-Effect Transistor), a gate insulating film (an oxide film) is formed to be extremely thin owing to the fine patterning in recent semiconductor devices. As a consequence, the gate insulating film is readily destroyed by the voltage of ESD. Accordingly, an ESD protection element usually is provided between a pad and the internal circuit (the circuit to be protected) in order to prevent the destruction of the semiconductor device by ESD.
A known ESD protection element utilizes the operation of a MOSFET-based parasitic bipolar transistor (e.g., see Patent Documents 1 and 2). In such an ESD protection element, a drain region is connected to the circuit to be protected and a source region (and gate electrode) is connected to a ground region or to a power-source region. For example, if an ESD current flows from a pad into the drain region in an n-type MOSFET-based ESD protection element, a reverse bias develops and avalanche breakdown occurs. A current then flows from the drain region to the silicon substrate, and the current raises the potential of the channel region. As a result, when the voltage of the base region surpasses a prescribed voltage, the device operates as a parasitic bipolar transistor in which the drain region is the collector, the silicon substrate is the base and the source region is the emitter. An ESC current therefore flows between the drain and source and is allowed to escape into the ground region.
When an ESD current flows into an ESD protection element, heat is evolved at the pn junction, e.g., between the drain and channel regions. In the ESD protection elements described in Patent Documents 1 and 2, regions of thermal dissipation (heat sinks) are formed in order to prevent destruction due to the evolution of heat. In the ESD protection element described in Patent Document 1, the heat dissipating regions are formed in such a manner that they will not become the path of an ESD current. The heat dissipating regions are separated from one another along the width direction of gate electrodes. In the ESD protection element described in Patent Document 2, a floating heat sink in which a direct electrical connection to the heat sink is non-existent is formed in the vicinity of a pn junction.
[Patent Document 1]
Japanese Patent Kokai Publication No. JP-P2005-311134A
[Patent Document 2]
U.S. Pat. No. 6,407,445